1. Field of the Invention
The present invention relates generally to the field of memory management and, more specifically, to a frame buffer managed dirty data pull and high-priority clean mechanism.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that serves as an intermediate point between an external memory (e.g., frame buffer memory) and internal clients of the memory subsystem (referred to herein as the “clients”). The L2 cache temporarily stores data that the clients are reading from and writing to the external memory (referred to herein as dynamic random access memory or “DRAM”).
In such a system, coherency has to be maintained between data present in the L2 cache and the data stored in the external memory. “Dirty data,” that is, data transferred from a client to the L2 cache during a write operation, needs to remain in the L2 cache until it has been “cleaned,” by replicating the data in the external memory. During a read operation, memory space is allocated within the L2 cache to receive the result data from the external memory. This allocated memory space remains unusable until the result data has been received from external memory by the L2 cache. Because the L2 cache receives a large number of write operations, substantial amounts of memory space in the data cache may be occupied with dirty data. Further read and write operations may be stalled until memory space becomes available in the L2 cache and applications, such as graphics processing, that require high data throughput may experience increased inefficiencies due to these issues.
As the foregoing illustrates, what is needed in the art is a technique to efficiently allocate memory space within an L2 cache for data associated with read and write operations.